Demand for erasable and programmable semiconductor memory devices capable of retaining data without a refresh function is on the rise. Further, attempts for improving the storage capacitance and integration of the memory device are increasing. A non-volatile memory device offers the large-scale storage capacity and high integration, without refresh of stored data, and one example of the device is a NAND-type flash memory device. Since the NAND-type flash memory device retains the data even in a case of power-off, it is widely used in applications where the possibility of power supply interruption is present such as portable terminal equipment, a portable computer, and so on.
Conventional non-volatile memory devices like the NAND-type flash memory device include a type of electrically erasable and programmable read-only memory (EEPROM) device typically referred to as “a flash EEPROM device.” Flash EEPROM devices generally include a semiconductor substrate (or bulk) of a first conductivity type, e.g. P-type; spaced source and drain regions of a second conductivity type, e.g. N-type, in the substrate; a channel region at a face of the substrate, between the spaced source and drain regions; a floating gate for storing charge carriers when the device is programmed; and a control gate which overlies the floating gate, opposite the channel region.
An array in the well-known NAND-type flash memory device is shown in FIG. 1. Referring to FIG. 1, the memory cell array 10 includes a plurality of cell strings 11 corresponding to bit lines. Here, two bit lines BL0 and BL1 and two cell strings 11 corresponding thereto are exemplified in FIG. 1, for the sake of convenience. Each of the cell strings 11 is composed of a string select transistor SST as a first select transistor, a ground select transistor GST as a second select transistor, and a plurality of EEPROM cells MC0 through MCm being serially connected between the select transistors SST and GST. The string select transistor SST has a drain connected to a corresponding bit line and a gate connected to string select line SSL. The ground select transistor GST has a source connected to a common source line CSL and a gate connected to a ground select line GSL. Between the source of the string select transistor SST and the drain of the ground select transistor GST, the flash EEPROM cells MCm-MC0 are serially connected, which are respectively connected to word lines WLm-WL0 corresponding thereto.
FIG. 2 is a timing diagram for describing a program method of the non-volatile memory device in FIG. 1.
Before describing a program method, as well known, the memory cells in the memory cell array 10 are erased at a certain threshold voltage, e.g. −1V. For the purpose of programming the memory cells, a high voltage, e.g. 20V, is applied to a word line of a selected memory cell for a predetermined time. Thus, the selected memory cell is charged to a higher threshold voltage while the threshold voltages of unselected memory cells remain unchanged.
Referring to FIG. 2, a ground path is blocked by applying 0V to the gate of the ground select transistor GST. A zero voltage (0V) potential is applied to a selected bit line, e.g., BL0, and a power supply voltage Vcc as the program inhibit voltage is applied to an unselected bit line, e.g., BL1. At the same time, a given voltage (e.g., the power supply voltage) is applied to the string select line, i.e., the gate of the string select transistor SST connected to the bit line BL1, which causes the source of the string select transistor SST (or the channel of a program inhibited cell transistor) to be charged up to Vcc-Vth (Vth is a threshold voltage of the string select transistor). Here, the string select transistor SST is substantially blocked or shut off. A time period for the aforementioned operation is referred to “a bit line setup period.”
Next, the channel voltage Vchannel of the program inhibited cell transistor is boosted by applying a high voltage, e.g. a program voltage Vpgm, to the selected word line, and applying a lower, e.g. a pass voltage Vpass, to the unselected word lines. Thus, Fowler-Nordheim (F-N) tunneling is prevented between a floating gate and the channel region. This retains the initial erased state of the program inhibited cell transistor. A time period for such an operation is referred to “a program period.” When a program voltage is applied to the word line, the voltage is applied not only to the selected memory cell but also to the unselected memory cells along the same word line for programming. Thus, the unselected memory cell, in particular the memory cell adjacent to the selected memory cell, is programmed. The unintentional programming of an unselected memory cell connected to a selected word line is referred to herein as “program disturb.”
One of the ways for preventing program disturb is a program inhibit method employing a self-boosting scheme. The program inhibit method employing the self-boosting scheme is disclosed in U.S. Pat. No. 5,677,873 entitled “Method of Programming Flash EEPROM Integrated Circuit Memory Devices to Prevent Inadvertent Programming of Nondesignated NAND memory cells therein.” and U.S. Pat. No. 5,991,202 entitled “Method for Reducing Program Disturb during Self-Boosting in a NAND flash Memory,” which are incorporated herein by reference.
After programming for the select memory cell is complete, a recovery operation for discharging charges of the bit line is performed.
The aforementioned program method has the following problem. As memory devices are scaled down, the space between adjacent signal lines is reduced. Thus, there arises capacitive coupling between adjacent signal lines through parasitic capacitance that exists between the adjacent signal lines. For example, when a program voltage Vpgm or a pass voltage Vpass is applied to a word line WLm adjacent to a string select line SSL (or located just below the string select line), as illustrated in FIG. 2, a voltage (e.g., Vcc) of the string select line SSL becomes higher than the power supply voltage Vcc due to capacitive coupling with the word line WLm. Due to the boosted voltage of the string select line SSL, charges that are charged by the self-boosting operation at a channel of a program inhibited cell transistor are leaked out to a bit line through the string select transistor (it is changed from a shut-off state to a turn-on state). That is, as illustrated in FIG. 2, a channel voltage Vchannel (or an inhibit voltage Vinhibit) of the program inhibited cell transistor is lowered by delta V (it is determined by a coupling ratio of a word line to a string select line and a program/pass voltage) in proportion to the boosted voltage of the string select line SSL. Therefore, program speed is dropped. This makes a threshold voltage distribution broader. Furthermore, the aforementioned program disturb may result.